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ATF16V8B
Features
* * *
Industry Standard Architecture Emulates Many 20-Pin PALs(R) Low Cost Easy-to-Use Software Tools High Speed Electrically Erasable Programmable Logic Devices 7.5 ns Maximum Pin-to-Pin Delay Several Power Saving Options
* * * * *
Device ATF16V8B ATF16V8BQ ATF16V8BQL
ICC, Stand-By 50 mA 35 mA 5 mA
ICC, Active 55 mA 40 mA 20 mA
CMOS and TTL Compatible Inputs and Outputs Input and I/O Pull-Up Resistors Advanced Flash Technology Reprogrammable 100% Tested High Reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 mA Latchup Immunity Commercial, and Industrial Temperature Ranges Dual-in-Line and Surface Mount Packages in Standard Pinouts
High Performance Flash PLD
ATF16V8B
Block Diagram
Description
The ATF16V8B is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel's proven electrically erasable Flash memory technology. Speeds down to 7.5 ns are offered. All speed ranges are specified over the full 5V 10% range for industrial temperature ranges, and 5V 5% for commercial temperature ranges. (continued)
Pin Configurations
Pin Name CLK I I/O OE VCC Function Clock Logic Inputs Bidirectional Buffers Output Enable +5V Supply
DIP/SOIC
PLCC
Top view
0364C
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Description (Continued)
Several low power options allow selection of the best solution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability.
The ATF16V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
Absolute Maximum Ratings*
Temperature Under Bias................. -55C to +125C Storage Temperature...................... -65C to +150C Voltage on Any Pin with Respect to Ground......................... -2.0V to +7.0V (1) Voltage on Input Pins with Respect to Ground During Programming.................... -2.0V to +14.0V (1) Programming Voltage with Respect to Ground....................... -2.0V to +14.0V (1)
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial Operating Temperature (Case) VCC Power Supply 0C - 70C 5V 5% Industrial -40C - 85C 5V 10%
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ATF16V8B
ATF16V8B
DC Characteristics
Symbol Parameter IIL IIH Input or I/O Low Leakage Current Input or I/O High Leakage Current Condition 0 VIN VIL (MAX) 3.5 VIN VCC B-7, -10 V = MAX, Power Supply Current, CC VIN = MAX, Standby Outputs Open B-15, -25 BQ-10 BQL-15, -25 ICC2 Clocked Power Supply VCC = MAX, Current Outputs Open BQL-15, -25 B-7, -10 V = MAX, Clocked Power Supply CC Outputs Open, Current f = 15 MHz B-15, -25 BQ-10 BQL-15, -25 IOS(1) VIL VIH VOL VOH Output Short Circuit Current Input Low Voltage Input High Voltage Output High Voltage Output High Voltage VIN = VIH or VIL, VCC = MIN VIN = VIH or VIL, VCC = MIN IOL = -24 mA Com., Ind. IOH = -4.0 mA 2.4 VOUT = 0.5V -0.5 2.0 Com. Ind. Com. Ind. Com. Com. Ind. Com. Ind. Com. Ind. Com. Ind. Com. Com. Ind. 55 55 50 50 35 5 5 1 1 60 60 55 55 40 20 20 90 100 85 95 55 35 40 -130 0.8 VCC + 0.75 0.5 Min Typ -35 Max -100 10 85 95 75 80 55 10 15 Units A A mA mA mA mA mA mA mA mA/MHz(2) mA/MHz(2) mA mA mA mA mA mA mA mA V V V V
ICC
ICC3
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. Low frequency only. See Supply Current versus Input Frequency curves.
1-9
AC Waveforms (1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics (1)
-7 (2) Symbol Parameter Input or Feedback to Non-Registered Output Clock to Feedback Clock to Output Input or Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tS+tCO) FMAX Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) tEA tER tPZX tPXZ Input to Output Enable -- Product Term Input to Output Disable -- Product Term OE pin to Output Enable OE pin to Output Disable 3 2 2 1.5 2 5 0 8 4 100 125 125 9 9 6 6 3 2 2 1.5 8 outputs switching 1 output switching
Min Max Min
-10
Max Min
-15
Max Min
-25
Max
Units ns ns
3
7.5 7 3 5
3
10
3
15
3
25
tPD
tCF tCO tS tH tP tW
6 2 7.5 0 12 6 68 74 83 10 10 10 10 3 2 2 1.5 7 2 12 0 16 8
8 10 2 15 0 24 12 45 50 62 15 15 15 15 3 2 2 1.5
10 12
ns ns ns ns ns ns
37 40 41 20 20 20 20
MHz MHz MHz ns ns ns ns
Notes: 1. See ordering information for valid part numbers and speed grades. 2. Recommend ATF16V8C-7.
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ATF16V8B
ATF16V8B
Input Test Waveforms and Measurement Levels: Output Test Loads:
Commercial
tR, tF < 5 ns (10% to 90%)
Pin Capacitance (f = 1 MHz, T = 25C) (1)
Typ CIN COUT
Note:
Max 8 8
Units pF pF
Conditions VIN = 0V VOUT = 0V
5 6
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the ATF16V8Bs are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1) The VCC rise must be monotonic, 2) After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3) The clock must remain stable during tPR.
Parameter Description tPR VRST Power-Up Reset Time Power-Up Reset Voltage
Typ 600
Max 1,000
Units ns
3.8
4.5
V
Preload of Registered Outputs
The ATF16V8B's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate.
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Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.
Input and I/O Pull-Ups
All ATF16V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to VCC. This ensures that all logic array inputs are at known states. These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below).
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming.
Input Diagram
I/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the ATF16V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF16V8B can be configured in one of three different modes. Each mode makes the ATF16V8B look like a different device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control. The ATF16V8B universal architecture can be programmed to emulate many 20-pin PAL devices. These architectural subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF16V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the content of the ATF16V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the Security Fuse.
Compiler Mode Selection
Registered ABEL, Atmel-ABEL CUPL LOG/iC OrCAD-PLD PLDesigner Tango-PLD
Note:
Complex P16V8C G16V8MA GAL16V8_C7 (1) "Complex" P16V8C G16V8C
Simple P16V8AS G16V8AS GAL16V8_C8 (1) "Simple" P16V8C G16V8AS
Auto Select P16V8 G16V8A GAL16V8 GAL16V8A P16V8A G16V8
P16V8R G16V8MS GAL16V8_R (1) "Registered" P16V8R G16V8R
1. Only applicable for version 3.4 or lower.
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ATF16V8B
ATF16V8B
Macrocell Configuration
Software compilers support the three different OMC modes as different device types. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output.
ATF16V8B Registered Mode
PAL Device Emulation / PAL Replacement The registered mode is used if one or more registers are required. Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently disabled. Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode: 16R8 16RP8 16R6 16RP6 16R4 16RP4
Registered Configuration for Registered Mode (1, 2)
Combinatorial Configuration for Registered Mode (1, 2)
Notes: 1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the registered outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the architecture control bits and checks for proper pin usage automatically.
Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the architecture control bits and checks for proper pin usage automatically.
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Registered Mode Logic Diagram
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ATF16V8B
ATF16V8B
ATF16V8B Complex Mode
PAL Device Emulation/PAL Replacement In the Complex Mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output. Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode: 16L8 16H8 16P8
Complex Mode Option
ATF16V8B Simple Mode
PAL Device Emulation / PAL Replacement In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs. The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs can be emulated using this mode: 10L8 12L6 14L4 16L2 10H8 12H6 14H4 16H2 10P8 12P6 14P4 16P2
Simple Mode Option
1-15
Complex Mode Logic Diagram
1-16
ATF16V8B
ATF16V8B
Simple Mode Logic Diagram
1-17
1-18
ATF16V8B
ATF16V8B
Note:
1. All normalized values referenced to maximum specification in AC Characteristics in the data sheet.
1-19
1-20
ATF16V8B
ATF16V8B
Ordering Information
tPD (ns) 7.5 tS (ns) 5 tCO (ns) 5 Ordering Code ATF16V8B-7JC (1) ATF16V8B-7PC (1) ATF16V8B-7SC (1) ATF16V8B-10JC ATF16V8B-10PC ATF16V8B-10SC ATF16V8B-10JI ATF16V8B-10PI ATF16V8B-10SI 15 12 10 ATF16V8B-15JC ATF16V8B-15PC ATF16V8B-15SC ATF16V8B-15JI ATF16V8B-15PI ATF16V8B-15SI 25 15 12 ATF16V8B-25JC ATF16V8B-25PC ATF16V8B-25SC ATF16V8B-25JI ATF16V8B-25PI ATF16V8B-25SI
Note: 1. Recommend ATF16V8C-7.
Package 20J 20P3 20S 20J 20P3 20S 20J 20P3 20S 20J 20P3 20S 20J 20P3 20S 20J 20P3 20S 20J 20P3 20S
Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
10
7.5
7
1-21
Ordering Information
tPD (ns) 10 tS (ns) 7.5 tCO (ns) 7 Ordering Code ATF16V8BQ-10JC ATF16V8BQ-10PC ATF16V8BQ-10SC ATF16V8BQL-15JC ATF16V8BQL-15PC ATF16V8BQL-15SC ATF16V8BQL-25JC ATF16V8BQL-25PC ATF16V8BQL-25SC ATF16V8BQL-25JI ATF16V8BQL-25PI ATF16V8BQL-25SI Package 20J 20P3 20S 20J 20P3 20S 20J 20P3 20S 20J 20P3 20S Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C)
15
12
10
25
15
12
Package Type
20J 20P3 20S
20 Lead, Plastic J-Leaded Chip Carrier (PLCC) 20 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
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ATF16V8B

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